1. Field of the Invention
The present invention relates to an information processing apparatus, a power saving controlling method and a storage medium, and more particularly to an information processing apparatus with a central processing unit and a main memory having a power saving mode, a power saving controlling method and a storage medium.
2. Description of the Related Art
Power saving type CPU's have been widely used in information processing apparatus having a power saving mode and a normal operation mode wherein the power saving mode is activated when a power saving mode transfer command (WAITI command) is executed and the operation mode is returned to the normal operation mode when a hardware interruption is input. In order to reduce a power consumption of the whole apparatus, a power saving mode is used for each of the constituent element of the system, and the power saving mode is activated for each constituent element not used during the operation of the apparatus.
A main memory for storing programs and data to be used by a CPU is a constituent element which consumes a large power. Various power saving modes for the main memory have been proposed. For example, the operation mode of a main memory using a synchronous DRAM (SDRAM) can be switched to a power saving mode by issuing a self refresh entry command (SELF command) to SDRAM.
Switching to such power saving mode is generally performed by the settings of CPU. In order to make the whole apparatus transfers to the power saving mode, first the main memory is required to transfer to the power saving mode by setting with CPU and then CPU itself is required to transfer to the power saving mode. However, in order for CPU itself to transfer to the power saving mode, it is necessary to execute a WAITI command. This WAITI command is generally stored in the main memory so that the main memory is required to be in the normal operation mode when the WAITI command is fetched.
When the operation mode is to be returned to the normal operation mode from the power saving mode by a hardware interruption, it is necessary for CPU first to make settings so that the main memory can recover the normal operation mode. However, immediately after CPU returns to the normal operation mode, CPU fetches a command for an interruption handler from the main memory. It is necessary that the main memory is in the normal operation mode at this time.
In order to satisfy the above-described requirements, in conventional arts, the main memory is divided into a static memory having a small capacity and a low consumption power such as a ROM and an SRAM, and an SDRAM having a large capacity. A routine for executing the WAITI command and an interruption handler are made always resident in the small capacity memory or they are transferred to the small capacity memory immediately before the transfer to the power saving mode.
In the information processing apparatus, it is generally necessary for CPU to fetch a command at a reset vector address immediately after the power is turned on. From this reason, the apparatus is provided with an inexpensive ROM (boot ROM) as a portion of the main memory. In a partial field of the boot ROM, the execution routine for the WAITI command and the interruption handler are fixedly written beforehand to configure the apparatus without providing a dedicated memory to the transfer to the power saving mode. Alternatively, if a CPU has a command cache, the operation mode is transferred to the power saving mode after the execution routine for the WAITI command and the interruption handler are locked down in the command cache. Namely, instead of using a dedicated SRAM, the command cache is used for the same purpose.
The above-conventional arts are, however, associated with the following problems. An inexpensive ROM has a longer access time than a RAM. Therefore, a command sequence in ROM is processed slower than a command sequence in RAM. If the interruption handler is fixedly written in ROM, not only a process regarding the transfer from the power saving mode but also a process regarding a usual interruption process becomes slow. This problem is critical for information processing apparatus, particularly those performing a real time process.
An approach to providing a dedicated SRAM results in a rise of the apparatus cost because of expensive SRAM.
An approach to utilizing a command cache results in a large process overhead and a low process speed, because each time the operation mode transfers to the power saving mode, a necessary routine or handler is locked down in the cache by using a specific cache operation command. Further, software for handling the cache is likely to become complicated and debugging is difficult. Locking down in the cache means a substantial reduction of the field for storing other commands, which results in a lower hit rate of the cache and a lower performance.